Lower gate delay and faster switching speed have long been among the design goals of field effect transistor (FET) devices, which are a basic building block of integrated circuits (ICs). One known technique for reducing gate delay and increasing switching speed (collectively “improving FET speed”) is a placement, in particular regions of certain FETs, of specifically structured stress-inducing elements. Such stress-inducing elements, also referred to in the semiconductor arts as “stressors,” induce particular mechanical stress in the crystalline lattice of the semi-conductor channel, between the source and drain, in certain structures of FETs. As known to persons of ordinary skill in the semiconductor arts, the stresses may increase the electron mobility, hence, improve the FET speed.
FET structures currently used, for example, in consumer products and various other applications include “planar” FETs and three-dimensional “FinFETs.” FinFETs can have certain advantages, for example, in overcoming the “short-channel” effects that can present when simply scaling down feature sizes of planar FETs. However, as has been known since FinFETs were introduced, a design objective they share with planar FETs is electron mobility. It has also been long known that certain of the stressor techniques that have proved useful in planar FETs may not be applicable to, or may incur particular costs when applied to FinFETs, particularly NMOS FinFETs.